1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to a buried trench capacitor and to a method of making the same.
2. Description of the Related Art
Modem integrated circuits routinely contain millions of individual transistors and other electronic components. Most of the interconnections for the numerous components in such circuits are provided via one or more metallization layers that serve as global interconnect levels. Each metallization layer is ordinarily deposited on the substrate of the integrated circuit as a single continuous layer that is thereafter patterned lithographically and etched to remove metal from areas where metal lines are not required.
One type of metal line almost universally found on integrated circuits is a power line or rail that supplies power to some or all of the various components making up the circuit. The power rail is connected to external power via one or more pins in a packaged part or via a bump, bonding wire or other structure in a flip-chip mounted part, and is normally biased between zero and some nominal voltage. In most integrated circuits implemented on a semiconductor substrate, the substrate itself serves as a companion rail to the power rail. In many circuits, the substrate is at ground. In others, such as many types of random access memory circuits, the substrate is negatively biased.
Power lines, like other types of conductors connected directly to input/output nodes of an integrated circuit are susceptible to significant noise interference. Noise or other unusual variations in power voltage may degrade device performance or even lead to damaging latch up conditions, particularly in complimentary metal oxide semiconductor ("CMOS") devices. Accordingly, it is desirable to connect a filter between the power rails of an integrated circuit, i.e., the power line or lines and the substrate. A capacitor is commonly selected to serve as the power rail filter. The substrate and a conductor layer function as the capacitor plates and a dielectric layer between the two functions as the capacitor dielectric.
In some conventional semiconductor processes, power filter capacitor fabrication involves formation of a local interconnect layer on top of trench isolation material, that is, above the silicon-silicon dioxide interface. For these types of capacitors, the substrate functions as one of the capacitor plates, the local interconnect layer serves as the other capacitor plate, and the trench isolation material serves as the capacitor dielectric. The thickness of the capacitor dielectric, and thus the potential capacitance, for such a filter capacitor is dictated by the depth or thickness of the trench isolation material. The depth of the trench isolation material is, in turn, dictated by design considerations other than the performance of filter capacitors, such as anticipated junction depths and substrate dopant concentration.
There are several disadvantages associated with conventional filter capacitor fabrication. In many processes, trench isolation material is formed to a depth of several thousand angstroms or more. The potential capacitance of a capacitor utilizing such a relatively thick layer as a capacitor dielectric is accordingly limited. While the deleterious effects of relatively large dielectric thickness can be offset somewhat by making the local interconnect larger, bigger local interconnects translate into the consumption of additional chip area.
In addition, each local interconnect layer formed above the silicon-silicon dioxide interface in a given integrated circuit represents a potential restriction on the routing of other conductor lines, and thus the packing density, for the circuit. The problem of routing restriction is more complex when doped polysilicon is used as the local interconnect material. Doped polysilicon is often selected for local interconnect layers as a result of thermal budgeting or other design considerations. The polysilicon is frequently used as both a gate material and local interconnect material. As a result, when the polysilicon layer functions as an interconnect structure, it cannot cross over regions where a transistor gate exists without making contact to the gate. Unless such contacts with the gates are desired, gate locations represent areas on the substrate that cannot be crossed by polysilicon layers where these layers are being used as local interconnect layers.
Various techniques to overcome the polysilicon routing restrictions have been implemented in the past. Some of these include selectively forming TiSi.sub.2 to form an LI level, sputter-depositing titanium-tungsten over CoSi.sub.2 contacts, forming a titanium nitride layer over a TiSi.sub.2 contact, and forming a dual-doped polysilicon LI with diffused source/drain junctions. While these techniques alleviate some of the routing difficulties associated with polysilicon local interconnect layers, they also increase processing steps and complexity. Furthermore, cluttering of the substrate area above the silicon-silicon dioxide interface remains a problem.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.